1. Field of the Invention
The present invention relates to a dynamic semiconductor memory device, and more particularly to a voltage dividing circuit in a one-transistor one-capacitor type dynamic semiconductor memory device for providing a switchable voltage to an electrode of the capacitor, to prevent errors during reading operations.
2. Description of the Prior Art
In general, a one-transistor one-capacitor type dynamic random access memory (RAM) includes one metal insulator semiconductor (MIS) transistor and one capacitor for each memory cell. The capacitor has one electrode connected to the transistor. The other electrode of the capacitor electrode (hereinafter referred to as the opposite electrode) was, in the earliest embodiments of this type of memory, connected to a power supply line or a ground line. Presently, however, the opposite electrode is usually connected to a point having a potential half that of the power supply potential V.sub.CC of the power supply line. The reason for connecting the opposite electrode to a point having the potential V.sub.CC /2 is as follows. Accompanied by recent improvements in the integration density of such semiconductor memory devices, the area of the electrodes of the capacitor in the memory cell has been more and more decreased. In order to obtain the desired capacitance with a capacitor having such a small area, the thickness of the insulating film between the electrodes of the capacitor is made thin. Because the insulating film is thin, the voltage tolerance of the insulating film is lowered. Therefore, the voltage applied between the electrodes of the capacitor is preferably small and is set to V.sub.CC /2 rather than V.sub.CC.
The present invention starts with such a conventional dynamic RAM as described above in which the opposite electrode of the capacitor in each memory cell is connected to a point having the potential V.sub.CC /2. Two resistors are conventionally used for providing the potential V.sub.CC /2. That is, two resistors having the same resistance are connected in series between the power supply line and the ground line so as to provide the potential V.sub.CC /2 at the function between the two resistors, and the opposite electrode of the capacitor in each memory cell is connected to the function between the resistors. In this construction, however, the potential of the opposite electrode fluctuates in response to internal clock signals or operation of the memory device due to parasitic capacitance in the memory device as described later in detail with reference to the drawings. Because countermeasures for the potential fluctuations of the opposite electrode are not provided in the conventional dynamic RAM, read errors often occur, as described later in detail.